A Compile-Time Managed Multi-Level Register File Hierarchy
Onur Mutlu on Twitter: "Our paper on latency-tolerant #GPU register file design presented by Amirhossein Mirhosseini at #asplos18: "LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching". Available at:
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PDF] Performance-centric register file design for GPUs using racetrack memory | Semantic Scholar
Performance-centric Register File Design for GPUs using Racetrack Memory